The present invention relates generally to data communications architecture and, more particularly, to asynchronous transfer mode (ATM) communication control apparatus for performing processing of low-level or infrastructure part of ATM protocols. The invention also relates to ATM controllers adaptable for use with the communication control apparatus in executing internal processing tasks thereof as well as control methods implementable therein.
ATM communication control apparatus is implemented and practiced for interconnection of a plurality of terminal units and communication lines of an ATM network operatively associated therewith to permit execution of communications between terminals pursuant to a preselected ATM protocol. More practically, an ATM communication control device is designed to execute processing at the infrastructure part of the ATM protocol in a way such that upon receipt of one or more variable length packets of information as generated at terminals, the controller divides each packet into a plurality of fixed length cells which are then transmitted to a communication line while simultaneously receiving cells from the line to generate one or more packets which are then passed to its intended terminal. Note that standardization of the ATM protocol per se is now in progress by the ATM Forum based on the recommendation of International Telecommunication Union (ITU).
One ATM controller is implemented using a large-scale integrated circuit (LSI) chip set which is designed to perform certain part of the processing tasks of the ATM communication control device, which may involve the processing of an ATM layer for cell transmit/receive operations and processing of an ATM adaptation layer (AAL) for subdivision and assembly of cells, namely, slicing and reconstruction, or alternatively, "segmentation" and "reassembly." A combination of such ATM layer processing and AAL layer processing will be referred to as the "ATM protocol processing" hereinafter. One example of such ATM controller may be the LSI microcomputer model .mu.PD98401/.mu.PD98402 used for ATM-LAN which has been disclosed in NEC Technical Bulletin Vol. 47, No. 7, 1994. This controller is designed to employ hard wired logic circuits that execute the ATM protocol processing through fixed or non-modifiable procedure routines. This architecture disclosed is capable of increasing performance. Unfortunately, this does not come without accompanying a penalty: functional inflexibility, that is, an inability to permit any change or alteration in content of processing once determined. The presently available ATM protocol is such that some processing parts still remain unstandardized, including the processing of administrative or "system management" cells which may be operation, administration and maintenance cells, these are collectively called the "OAM" cells among those skilled in the art, for use in routine maintenance and handling operations, plus resource management (RM) cells for use in controlling the congestion of traffic over communication links. It is desirable that ATM controllers be capable of accommodating any possible changes and alterations of such parts unstandardized.
One exemplary ATM controller capable of accommodating the need for processing alterations is the device called "ATMizer" which has been disclosed in a Japanese publication "NIKKEI Electronics", August 1994 at pages 1-4. This ATM controller disclosed comes with a built-in microprocessor for execution of software-based processing tasks to handle many parts of the ATM protocol processing, including cell header analysis, cell segmentation/reassembly processes and others.